Neural networks have been used for many years in a variety of applications, from engineering and robotics to business and economics. Due to the cellular configuration of neural networks, they are ideally implemented in electronic circuits, where the processing is distributed throughout the entire network. Minsky created the first electronic neural network for use in a robot (“SNARC”) in 1951 [28]. Since then, various researchers have attempted to create VLSI chips to emulate neural networks [2], [3], [5], [9], [15], [16], [18], [32].

The design of this novel adaptive chip is a significant improvement over previously proposed networks. Using analog VLSI CMOS technology, accurate arithmetic function circuits are densely distributed throughout the chip. Multiple parameters, including learning rate, are stored in each neuron and synapse cell using a unique high-resolution analog memory technique. Forwards- and backwards- propagation are implemented, allowing on-chip learning with either Backpropagation or Hebbian learning algorithms.

A unique aspect of this project involves the design of improved learning algorithms to take advantage of the features provided by CMOS implementation of the neural network. An external FPGA-based “supervising controller” [15] is required to implement these extended algorithms, based on the monitoring and modification of stored parameters.

Copyright © Malcolm Stagg 2006. All Rights Reserved.
Website: http://www.virtualsciencefair.org/2006/stag6m2. Email: malcolmst@shaw.ca.