Procedure

1) Design algorithms for improved learning using the supervising controller

2) Plan out general neural network layout, including routing connections

3) Plan out block diagrams for each cell (neuron, synapse, etc…)

4) Design and simulate schematics for each sub-cell (multiplier, sigmoid, etc…)

5) Propose improved method of analog memory, with higher resolution and better density than existing methods

6) Introduce a CMOS 0.35um layout for each sub-cell, and combine together to form cell designs

7) Layout and build circuit board for prototype demonstration

8) Create software for chip routing and control

9) Collect and analyze results of the performance of the new learning algorithms

Copyright © Malcolm Stagg 2006. All Rights Reserved.
Website: http://www.virtualsciencefair.org/2006/stag6m2. Email: malcolmst@shaw.ca.