|A Dynamic Analog Concurrently-Processed Adaptive Chip|
|By Malcolm Stagg|
Routing within the chip consists of a new configuration of programmable connections and programmable wires, diagonally between neuron/synapse cells. At each location, a square array of programmable connections is surrounded by programmable wires. This allows the chip to be routed as if it were a circuit board, with horizontal and vertical layers containing multiple traces between neuron/synapse cells, which can be connected with vias, and traces which can be ended at any point.
Programmable connections are used as vias between the horizontal and vertical layers, and programmable wires are used to end the traces at any point.