The refresh controller allows analog memory cells distributed throughout the chip to maintain stored values to high accuracy. Due to inherent leakage of analog capacitor cells, 3 capacitors are used to store each value to 11-bit resolution. One of the capacitors stores all 11-bits, but only 3-bits are used for quantization, plus 1 for error-checking. Two of the capacitors store signals to 4-bit resolution.

Quantization takes place by comparing stored values to a global 4-bit ramp signal. Signals are refreshed to the nearest discrete level greater than the stored level.

Method 1: Fully Analog

To combine the signals together, a modified form of a Digital-to-Analog Converter is used. This new device is called a Multivalued-to-Analog Converter, due to the fact that the inputs are in fact quantized analog. Global ramps are used in the quantization of the LSB (least significant bit) capacitors, by comparing two ramp levels to the stored value. If the value falls between the two values, it will be adjusted to fall on a valid level. LSB capacitors are combined together with a multivalued-to-analog converter (e.g. [3b][4b][4b] to form an 11-bit signal with 3 capacitors). The first capacitor stores the entire signal, but a few bits can only be used in the quantization due to leakage.

See Also: Multivalued-to-Analog Converter

These circuits handle refresh of existing signals, however, weight update must still be performed. For this to take place, an additional controller should be placed in each refresh controller to add together weight and weight update, and quantize that value using the ramp signals. This is effectively an analog-to-multivalued converter (as opposed to analog-to-digital).

Method 2: Analog/Digital

This is very similar to the method proposed by Lee and Gulak in 1991 and 1992 [19], [22]. Using a capacitor based memory cell for a few MSBs (Most Significant Bits), and digital SRAM for LSBs (Least Significant Bits), the full signal can be reconstructed with better density than having the entire signal in digital SRAM. While this may have better density than method 1, since method 1 must contain several large capacitors to store the signal, more space is used in routing, and the refresh controller must be somewhat larger and more complex, in that digital refresh circuitry is mostly used. Process parameters must be examined to find which method would have better density.

SRAM does not need to be refreshed, but the analog capacitor-based memory cell requires a frequent refresh to avoid data loss. It is refreshed using an ADC (Analog-to-Digital Converter) to find the value of the analog memory cell to several bits, and a DAC (Digital-to-Analog Converter) to refresh the analog memory cell. Due to leakage, there must be a 1-bit overlap between the analog and digital cells. If the bits do not match, then it is known that the analog memory cell is off by 1-bit, and must be adjusted digitally.

Weight updates are computed by adding the weight to the stored capacitor in analog, then using an ADC to find the new values for the digital signals, with a ramp used for detecting the new analog MSBs.

Method 3: Fully Digital

This method is very similar to method 2, except having all bits of the signal in digital SRAM. This has an advantage in terms of refresh speed, that the analog refresh rate is not critical to avoid data loss. It however requires additional area for SRAM cells and routing.

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