A Dynamic Analog Concurrently-Processed Adaptive Chip
By Malcolm Stagg
Chip Overview
Please click an area of the chip to continue.

Note: diagram is not to scale.
I/O Pins I/O Pins I/O Pins I/O Pins Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Synapse Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Synapse Routing Vector Neuron Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Routing Vector Routing Array Refresh Controller Row Decoder Column Decoder Global Signals
  1. I/O Pins
  2. Routing Array
  3. Routing Vector
  4. Neuron
  5. Synapse
  6. Refresh Controller
  7. Row Decoder
  8. Column Decoder
  9. Global Signals