Basic arithmetic circuits required for neural networks can be implemented in analog VLSI (Very Large Scale Integration) CMOS (Complementary Metal Oxide Semiconductor) process using only a few transistors. The basic nonlinear sigmoid circuit of tanh [25] can be put in as a simple differential pair. The derivative of tanh (required for backwards-propagation) as sech2 [11] is identical, except with a different layout of the two output transistors.
The proposed neuron design supports both Backpropagation and Hebbian learning on the same cell. Differential currents are summed at the input, and converted into voltages. The voltages are input into the tanh sigmoid and sech2 sigmoid derivative. The tanh is output from the neuron as a differential voltage. An analog memory averaging cell stores the moving average of the sigmoid output. A multiplier cell calculates the product of the backwards-propagating input and the sech2 of the input signal. An SRAM cell is used to store whether BP or Hebbian is used. If BP is used, the multiplier output is connected to the backwards propagation output using a transmission gate. If Hebbian is used, transmission gates connect both backwards-propagating input and output to the single-ended sigmoid output minus the single-ended average, as a differential voltage.
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Proposed Multi-Algorithm Neuron Block Diagram |
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Proposed Multi-Algorithm Neuron Cell Layout |
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