Abstract

The purpose of this project is to overcome the limitations of current neural network chips which generally have poor reconfigurability, and lack parameters for efficient learning. A new general-purpose analog neural network design is made for the TSMC 0.35um CMOS process. Parallel processing is possible with a massive array of independent cells, concurrently processing data. This allows the network to quickly recognize information in various applications. With support for multiple learning algorithms, arbitrary routing, high density, and storage of many parameters using improved high-resolution analog multi-valued memory, this network is suitable for vast improvements to the learning algorithms. Such improvements allow learning to interact with routing for a network which is not bound to a fixed layout. Other improvements include the interaction of multiple learning algorithms to learn partially by pattern, and partially by feedback.
Modified Backpropagation learning used with the learning rate parameters allows important data to be reinforced and retained, and insignificant data to be labile, providing improved learning speed. In addition to introducing the planned design for chip implementation, an op-amp prototype is created on a PC board. This prototype allows further development at cell-level, as well as a demonstration of the operation of the CMOS chip. SPICE is used for simulations of the CMOS circuit cells to determine accuracy and input/output range. Neuron circuits were found to be accurate, as was the Gilbert multiplier when input range was restricted. Neuron and synapse circuit design is complete, now in the simulation and layout phase.

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Copyright © Malcolm Stagg 2006. All Rights Reserved.
Website: http://www.virtualsciencefair.org/2006/stag6m2. Email: malcolmst@shaw.ca.